`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/10/28 22:16:36
// Design Name: 
// Module Name: trigger
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module trigger #(
    parameter reg_cnt = 4
)(
    input 				        clk	,	//系统时钟
    input                       rst_n,
    input       [reg_cnt-1:0]   signal,
    output  reg                 signal_vld,
    output  reg [reg_cnt-1:0]   signal_trigger
);

reg [reg_cnt-1:0]   signal_1;
always @ (posedge clk or negedge rst_n)begin
    if(rst_n==1'b0)begin
        signal_1<=0;
        signal_trigger <= 0;
        signal_vld<=0;
    end
    else begin
        signal_vld<=1;
        signal_1<=signal;
        signal_trigger <= signal&(~signal_1);
    end
end










endmodule
